The present invention relates generally to apparatuses and methods for performing metastabilty analyses of designs which include one or more synchronous elements. The present invention more specifically relates to an apparatus and method which can be used to assess whether a design presents a metastability risk.
Typically, simulation tests, such as best case and worst case simulations, are performed on designs which contain one or more synchronous elements. These simulations produce one or more simulation files (e.g. print on change files) which contain information regarding times at which data and clock signals changed during the simulation. This information can be reviewed to determine whether the design is acceptable.
Best and worst case simulations may indicate that either the data signal or the clock signal leads the other with plenty of margin. For example, best case simulations may show the data signal leading the clock signal with plenty of margin, and worst case simulations may show the clock signal leading the data signal with plenty of margin. Both of these conditions may be acceptable for the system function. However, if data and clock of a synchronous element reverse position over best and worst case, it is a definite metastability risk because at some point in time, the data and clock signals transition at the same time.
A metastability risk may result from either internal or external conditions. Internal metastability issues are caused by clock and data paths that cross each other over temperature, process and voltage. Externally driven metastability risks may result due to clock being asynchronous with respect to data, or due to externally driven signals having large delay shifts over temperature, process and voltage. These delay shifts may be due to long interconnect routes from the I/O ring to the core logic.
Unless great care is taken, metastability risks may exist within a design without a designer""s knowledge. Since simulations, such as worst case and best case simulations, are discreet points and are digital in nature, they may not identify metastability risks. Unless a simulation is run at the proper condition, a setup or hold time violation may not occur during the simulation even though a potential metastability condition exists.
Metastability is not acceptable for system performance and may even cause an intermittent system failure. Additionally, metastability can cause serious system level problems that are very difficult to debug. As a result, metastability issues could result in lengthy debug efforts, unnecessary redesigns and costly design schedule impacts.
It is desirable to know whether a design is at risk for metastability, and which synchronous elements in a design present metastability risks. If a designer were to know which synchronous elements in a design present a metastability risk, the designer could take corrective action. For example, the designer could change the path delays such that the data and clock signals no longer cross over each other, or the designer could replace the synchronous element with a synchronizer cell that is less susceptible to metastability, thus minimizing the overall risk of metastability. The designer could also use the tool as a debug device once metastability is suspected in silicon.
It is an object of the present invention to provide an apparatus and method which can be used to assess whether a design presents a metastability risk.
It is a further object of the present invention to provide an apparatus and method for analyzing simulation information to identify metastability risks of a design.
In accordance with these and other objects, the present invention provides a metastability risk simulation analysis device and a method of using a metastability risk simulation analysis device to identify metastability risks of a design. The metastability risk simulation analysis device includes computer readable code which is configured to analyze simulation information relating to the design and determine whether the design presents a metastability risk.
Desirably, the computer readable code is configured to determine whether two signals, such as a data signal and a clock signal of a synchronous element of the design, cross over each other thereby presenting a metastability risk, and is configured to generate a summary report identifying those synchronous elements of the design which present a metastability risk. Preferably, the computer readable code is configured to analyze simulation information relating to best case and worst case simulations of the design, and is configured to scan the simulation information to identify an edge of a clock signal and an edge of a data signal of the best case and worst case simulations and determine whether the signals cross each other.
Preferably, the computer readable code is configured to scan the simulation information to identify an edge of a clock signal of the best case simulation and associate a data search window on the edge of the clock signal of the best case simulation, and the computer readable code is configured to scan the data search window associated on the edge of the clock signal of the best case simulation to determine whether the data signal of the best case simulation transitions within the data search window. Also, preferably the computer readable code is configured to determine how much the data signal and clock to signal of the best case simulation lead each other, is configured to associate a clock search window on the edge of the clock signal of the best case simulation, and is configured to scan the clock search window associated with the edge of the clock signal of the best case simulation to determine whether the clock signal of the worst case simulation transitions within the clock search window. Still further, preferably the computer readable code is configured to associate a data search window on the edge of the clock signal of the worst case simulation, and is configured to scan the data search window associated with the edge of the clock signal of the worst case simulation to determine whether the data signal of the worst case simulation transitions within the data search window. Still even further, preferably the computer readable code is configured to determine how much the data signal and clock signal of the worst case simulation lead each other, and is configured to determine whether the data signals and clock signals cross over each other from the best case simulation to the worst case simulation. Ideally, the computer readable code is configured to analyze simulation information relating to best case and worst case simulations of the design with regard to a plurality of synchronous elements of the design.